{"id":40076,"date":"2025-12-02T09:51:00","date_gmt":"2025-12-02T02:51:00","guid":{"rendered":"https:\/\/thaipropertynews.com\/feeds\/?p=40076"},"modified":"2025-12-02T09:51:00","modified_gmt":"2025-12-02T02:51:00","slug":"digitimes-asia-ai-workload-surge-creates-opening-for-alternative-memory-and-chiplet-technologies-expert-says","status":"publish","type":"post","link":"https:\/\/thaipropertynews.com\/feeds\/?p=40076","title":{"rendered":"DIGITIMES ASIA: AI workload surge creates opening for alternative memory and chiplet technologies, expert says"},"content":{"rendered":"

TAIPEI<\/span>, Dec. 2, 2025 \/PRNewswire\/ — The rapid expansion of artificial intelligence (AI) workloads is forcing a fundamental redesign of data center infrastructure, driving historic memory shortages and opening a rare market window for alternative memory technologies, according to Chuck\u00a0Sobey, founder of ChannelScience and general chair of the Chiplet Summit.<\/span><\/p>\n

\n

\"Credit:<\/a>
Credit: Digitimes<\/span><\/p>\n<\/div>\n

Speaking on the industry’s shift, Sobey highlighted that AI workloads differ structurally from traditional enterprise tasks. While legacy workloads stress the CPU, network, and storage\u2014often leaving processors waiting for I\/O\u2014modern AI tasks, such as deep learning training, large language model (LLM) inference, and retrieval-augmented generation (RAG), are critically bound by memory bandwidth.<\/p>\n

The bandwidth gap and power crisis<\/b><\/p>\n

The demands of the AI era are unprecedented. Sobey noted that AI systems can require up to 10 terabytes per second (TB\/s) of GPU memory access\u2014roughly 50 to 200 times the bandwidth of standard DDR5. Unlike web and cloud requests that deal in kilobytes, AI accesses involve gigabyte-sized tensors, necessitating algorithms that exercise the entire memory storage hierarchy.<\/p>\n

This architectural strain has profound economic consequences. Sobey described the modern AI data center as a “token<\/span> factory,” where revenue is derived strictly from processing tokens. Currently, these facilities are power-limited and memory-limited rather than compute-limited. Power density requirements are skyrocketing, forcing rack redesigns to support up to one megawatt\u2014exceeding previous standards by 10 to 100 times.<\/p>\n

Supply chains are already buckling under this pressure. Sobey pointed to a historic shortage in the memory sector, specifically for high-performance server memory, with reports of a 70% fulfillment rate for orders and price surges of up to 50%. Securing necessary memory inventory is becoming increasingly difficult for all but the largest hyperscalers.<\/p>\n

Chiplets: the gateway for MRAM and RRAM<\/b><\/p>\n

Sobey identified this supply\/power crunch as a strategic entry point for “alternative memories”\u2014technologies like MRAM (magnetoresistive RAM), RRAM (resistive RAM), and phase change memory (PCM) that lack the dedicated, multi-billion-dollar fabs of incumbents.<\/p>\n

The chiplet architecture is the critical enabler for this transition. By disaggregating functions from monolithic ASICs into smaller units, chiplets allow designers to integrate esoteric materials required for alternative memory without contaminating high-end logic fabrication processes. This heterogeneous integration allows for specific performance advantages, such as radiation tolerance or high-temperature resilience, which Sobey argues are necessary differentiators beyond simple cost claims.<\/p>\n

The new “five-second rule”<\/b><\/p>\n

The velocity of AI is also compressing economic rules of thumb. Sobey observed that the long-standing “five-minute rule”\u2014which dictates data should be kept in DRAM if accessed within five minutes\u2014has accelerated to a “five-second rule.” In the AI era, if data is not accessed within five seconds, the cost-benefit analysis dictates it must be ejected from expensive, fast memory tiers.<\/p>\n

Sobey said the current surge in AI is no mere ripple but a gathering wave, arguing that suppliers need to secure their positions now if they hope to retain an edge when pricing and supply chains eventually settle.<\/p>\n

Sobey will discuss the impact of chiplets on the memory-storage hierarchy further during the\u00a0DIGITIMES\u00a0webinar<\/a><\/i><\/b> on December 5, 2025<\/span>, and at the Chiplet Summit<\/b> in Santa Clara, California<\/span>, scheduled for February 17\u201319, 2026.<\/p>\n

<\/div>","protected":false},"excerpt":{"rendered":"

<\/p>\n

TAIPEI<\/span>, Dec. 2, 2025 \/PRNewswire\/ — The rapid expansion of artificial intelligence (AI) workloads is forcing a fundamental redesign of data center infrastructure, driving historic memory shortages and opening a rare market window for alternative memory technologies, according to Chuck\u00a0Sobey, founder of ChannelScience and general chair of the Chiplet Summit.<\/span><\/p>\n

\n

\"Credit:<\/a>
Credit: Digitimes<\/span><\/p>\n<\/div>\n

Speaking on the industry’s shift, Sobey highlighted that AI workloads differ structurally from traditional enterprise tasks. While legacy workloads stress the CPU, network, and storage\u2014often leaving processors waiting for I\/O\u2014modern AI tasks, such as deep learning training, large language model (LLM) inference, and retrieval-augmented generation (RAG), are critically bound by memory bandwidth.<\/p>\n

The bandwidth gap and power crisis<\/b><\/p>\n

The demands of the AI era are unprecedented. Sobey noted that AI systems can require up to 10 terabytes per second (TB\/s) of GPU memory access\u2014roughly 50 to 200 times the bandwidth of standard DDR5. Unlike web and cloud requests that deal in kilobytes, AI accesses involve gigabyte-sized tensors, necessitating algorithms that exercise the entire memory storage hierarchy.<\/p>\n

This architectural strain has profound economic consequences. Sobey described the modern AI data center as a “token<\/span> factory,” where revenue is derived strictly from processing tokens. Currently, these facilities are power-limited and memory-limited rather than compute-limited. Power density requirements are skyrocketing, forcing rack redesigns to support up to one megawatt\u2014exceeding previous standards by 10 to 100 times.<\/p>\n

Supply chains are already buckling under this pressure. Sobey pointed to a historic shortage in the memory sector, specifically for high-performance server memory, with reports of a 70% fulfillment rate for orders and price surges of up to 50%. Securing necessary memory inventory is becoming increasingly difficult for all but the largest hyperscalers.<\/p>\n

Chiplets: the gateway for MRAM and RRAM<\/b><\/p>\n

Sobey identified this supply\/power crunch as a strategic entry point for “alternative memories”\u2014technologies like MRAM (magnetoresistive RAM), RRAM (resistive RAM), and phase change memory (PCM) that lack the dedicated, multi-billion-dollar fabs of incumbents.<\/p>\n

The chiplet architecture is the critical enabler for this transition. By disaggregating functions from monolithic ASICs into smaller units, chiplets allow designers to integrate esoteric materials required for alternative memory without contaminating high-end logic fabrication processes. This heterogeneous integration allows for specific performance advantages, such as radiation tolerance or high-temperature resilience, which Sobey argues are necessary differentiators beyond simple cost claims.<\/p>\n

The new “five-second rule”<\/b><\/p>\n

The velocity of AI is also compressing economic rules of thumb. Sobey observed that the long-standing “five-minute rule”\u2014which dictates data should be kept in DRAM if accessed within five minutes\u2014has accelerated to a “five-second rule.” In the AI era, if data is not accessed within five seconds, the cost-benefit analysis dictates it must be ejected from expensive, fast memory tiers.<\/p>\n

Sobey said the current surge in AI is no mere ripple but a gathering wave, arguing that suppliers need to secure their positions now if they hope to retain an edge when pricing and supply chains eventually settle.<\/p>\n

Sobey will discuss the impact of chiplets on the memory-storage hierarchy further during the\u00a0DIGITIMES\u00a0webinar<\/a><\/i><\/b> on December 5, 2025<\/span>, and at the Chiplet Summit<\/b> in Santa Clara, California<\/span>, scheduled for February 17\u201319, 2026.<\/p>\n

<\/div>\n

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