{"id":15362,"date":"2024-12-19T11:43:05","date_gmt":"2024-12-19T04:43:05","guid":{"rendered":"https:\/\/thaipropertynews.com\/feeds\/?p=15362"},"modified":"2024-12-19T11:43:05","modified_gmt":"2024-12-19T04:43:05","slug":"s2c-launches-prodigy-s8-100-series-100m-gate-fpga-prototyping-for-ai-and-hpc-2","status":"publish","type":"post","link":"https:\/\/thaipropertynews.com\/feeds\/?p=15362","title":{"rendered":"S2C Launches Prodigy S8-100 Series: 100M Gate FPGA Prototyping for AI and HPC"},"content":{"rendered":"

SAN JOSE, Calif.<\/span><\/span>, Dec. 19, 2024<\/span><\/span> \/PRNewswire\/ —\u00a0S2C, a global leader in FPGA-based prototyping solutions, announces its Prodigy S8-100 Logic System<\/b>, the latest addition to the eighth-generation family, is shipping and deployed by leading enterprises. <\/b>Designed to address the growing demands of AI and HPC, the S8-100 series delivers unparalleled scalability, flexibility, and efficiency.<\/p>\n

Powered by AMD Versal\u2122 Premium VP1902 adaptive SoC with 100M<\/span> ASIC gate capacity<\/b>, the S8-100 delivers 2x logic resources<\/b> and 2.5x the I\/O bandwidth<\/b> when\u00a0compared with its predecessor\u00a0S7-19P.\u00a0Available in Single, Dual, and Quad FPGA configurations<\/b>, the S8-100 supports medium-scale to hyperscale designs with ease, making it a versatile choice for advanced chip development.<\/p>\n

Highlights:<\/b><\/p>\n

Rich Resources: <\/b>The S8-100 delivers remarkable resources, featuring 18,507K<\/span> system logic cells, 858Mb of internal memory, 6,864 DSP slices, dual-core Arm Cortex A72 and dual-core Arm Cortex R5 in each FPGA module.<\/p>\n

High-Speed & Flexible I\/O Architecture:<\/b> Equipped with 2,212 XPIOs supporting dynamic I\/O voltages (1.0V\u20131.5V) and GTM\/GTYP transceivers with PCIe\u00a0Gen5\u00a0and data rates of up to 56Gbps, the S8-100 effortlessly meets a wide range of system requirements.<\/p>\n

Scaling and Partitioning Made Easy: <\/b>PlayerPro-CT partitioning software supports TDM-driven, multi-strategy scheduling and placements. Fully automated flow takes RTL to bitstream with simple clicks, significantly boosting productivity.<\/p>\n

High Productivity Toolchain: <\/b>Add-on tools, including PlayerPro-DT for multi-FPGA debugging, ProtoBridge for co-simulation, and an extensive library of Prototype Ready IP of pre-validated daughter cards, speed adapters, memory interface models and reference designs, accelerate deployment and shorten the development cycle.<\/p>\n

The S8-100 Logic System, with a capacity of 100M<\/span> ASIC gates per FPGA, doubles the resources of its predecessor, the S7-19P, and offers a 2.5x increase in I\/O bandwidth. Featuring high I\/O counts and 32\/56Gbps transceivers supporting protocols such as PCIe Gen5 and QSFP-DD, it combines robust performance with flexible scalability, meeting the demands of complex logic designs.<\/p>\n

In particular, advanced RISC-V cores can comfortably fit inside a single S8-100 system without the need to partition. A three to five times boost in performance can be expected. For hyperscale AI and HPC designs, the S8-100 reduces partitioning complexity, simplifies topology, and facilitates seamless optimization.<\/p>\n

To accelerate deployment, S2C offers a library of ready-to-use daughter cards, memory adapters, speed adapters, and reference designs. These tools streamline the setup of validation environments and simplify system integration. Frequently adopted options include high-speed PCIe Gen5, 400G Ethernet, and LPDDR\/DDR5, and common SoC interfaces such as QSPI, MIPI D-PHY, and JTAG\/debug, matching the needs across diverse applications.<\/p>\n

Combining the S8-100 with fully automated timing-driven partitioning software enables one-click flow from RTL to bitstream, simplifying the steps of large design partitioning. S2C’s robust toolchain, including real-time control (Player Pro-RunTime), multi-debugging (Player Pro-DebugTime) and co-simulation (ProtoBridge), significantly boosts productivity, making it an essential tool for complex chip design.<\/p>\n

“The era of AI has begun, and chip design is getting ever more difficult to keep up.” said Ying\u00a0J\u00a0Chen, VP of marketing. “Prodigy S8-100 with expanded capacity and superior performance is here to provide a robust verification solution for innovation in AI and HPC.<\/p>\n

Availability<\/b><\/p>\n

The Prodigy S8-100 Series (Single\/Dual\/Quad) is shipping now<\/b>. For more information, please contact your local S2C representative or visit www.s2cinc.com<\/a><\/b>.<\/p>","protected":false},"excerpt":{"rendered":"

<\/p>\n

SAN JOSE, Calif.<\/span><\/span>, Dec. 19, 2024<\/span><\/span> \/PRNewswire\/ —\u00a0S2C, a global leader in FPGA-based prototyping solutions, announces its Prodigy S8-100 Logic System<\/b>, the latest addition to the eighth-generation family, is shipping and deployed by leading enterprises. <\/b>Designed to address the growing demands of AI and HPC, the S8-100 series delivers unparalleled scalability, flexibility, and efficiency.<\/p>\n

Powered by AMD Versal\u2122 Premium VP1902 adaptive SoC with 100M<\/span> ASIC gate capacity<\/b>, the S8-100 delivers 2x logic resources<\/b> and 2.5x the I\/O bandwidth<\/b> when\u00a0compared with its predecessor\u00a0S7-19P.\u00a0Available in Single, Dual, and Quad FPGA configurations<\/b>, the S8-100 supports medium-scale to hyperscale designs with ease, making it a versatile choice for advanced chip development.<\/p>\n

Highlights:<\/b><\/p>\n

Rich Resources: <\/b>The S8-100 delivers remarkable resources, featuring 18,507K<\/span> system logic cells, 858Mb of internal memory, 6,864 DSP slices, dual-core Arm Cortex A72 and dual-core Arm Cortex R5 in each FPGA module.<\/p>\n

High-Speed & Flexible I\/O Architecture:<\/b> Equipped with 2,212 XPIOs supporting dynamic I\/O voltages (1.0V\u20131.5V) and GTM\/GTYP transceivers with PCIe\u00a0Gen5\u00a0and data rates of up to 56Gbps, the S8-100 effortlessly meets a wide range of system requirements.<\/p>\n

Scaling and Partitioning Made Easy: <\/b>PlayerPro-CT partitioning software supports TDM-driven, multi-strategy scheduling and placements. Fully automated flow takes RTL to bitstream with simple clicks, significantly boosting productivity.<\/p>\n

High Productivity Toolchain: <\/b>Add-on tools, including PlayerPro-DT for multi-FPGA debugging, ProtoBridge for co-simulation, and an extensive library of Prototype Ready IP of pre-validated daughter cards, speed adapters, memory interface models and reference designs, accelerate deployment and shorten the development cycle.<\/p>\n

The S8-100 Logic System, with a capacity of 100M<\/span> ASIC gates per FPGA, doubles the resources of its predecessor, the S7-19P, and offers a 2.5x increase in I\/O bandwidth. Featuring high I\/O counts and 32\/56Gbps transceivers supporting protocols such as PCIe Gen5 and QSFP-DD, it combines robust performance with flexible scalability, meeting the demands of complex logic designs.<\/p>\n

In particular, advanced RISC-V cores can comfortably fit inside a single S8-100 system without the need to partition. A three to five times boost in performance can be expected. For hyperscale AI and HPC designs, the S8-100 reduces partitioning complexity, simplifies topology, and facilitates seamless optimization.<\/p>\n

To accelerate deployment, S2C offers a library of ready-to-use daughter cards, memory adapters, speed adapters, and reference designs. These tools streamline the setup of validation environments and simplify system integration. Frequently adopted options include high-speed PCIe Gen5, 400G Ethernet, and LPDDR\/DDR5, and common SoC interfaces such as QSPI, MIPI D-PHY, and JTAG\/debug, matching the needs across diverse applications.<\/p>\n

Combining the S8-100 with fully automated timing-driven partitioning software enables one-click flow from RTL to bitstream, simplifying the steps of large design partitioning. S2C’s robust toolchain, including real-time control (Player Pro-RunTime), multi-debugging (Player Pro-DebugTime) and co-simulation (ProtoBridge), significantly boosts productivity, making it an essential tool for complex chip design.<\/p>\n

“The era of AI has begun, and chip design is getting ever more difficult to keep up.” said Ying\u00a0J\u00a0Chen, VP of marketing. “Prodigy S8-100 with expanded capacity and superior performance is here to provide a robust verification solution for innovation in AI and HPC.<\/p>\n

Availability<\/b><\/p>\n

The Prodigy S8-100 Series (Single\/Dual\/Quad) is shipping now<\/b>. For more information, please contact your local S2C representative or visit www.s2cinc.com<\/a><\/b>.<\/p>\n

<\/p>\n","protected":false},"author":0,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"rop_custom_images_group":[],"rop_custom_messages_group":[],"rop_publish_now":"initial","rop_publish_now_accounts":[],"rop_publish_now_history":[],"rop_publish_now_status":"pending","footnotes":""},"categories":[5,7],"tags":[],"class_list":["post-15362","post","type-post","status-publish","format-standard","hentry","category-cision-pr-newswire","category-cision-pr-newswire-en"],"_links":{"self":[{"href":"https:\/\/thaipropertynews.com\/feeds\/index.php?rest_route=\/wp\/v2\/posts\/15362","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/thaipropertynews.com\/feeds\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/thaipropertynews.com\/feeds\/index.php?rest_route=\/wp\/v2\/types\/post"}],"replies":[{"embeddable":true,"href":"https:\/\/thaipropertynews.com\/feeds\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=15362"}],"version-history":[{"count":0,"href":"https:\/\/thaipropertynews.com\/feeds\/index.php?rest_route=\/wp\/v2\/posts\/15362\/revisions"}],"wp:attachment":[{"href":"https:\/\/thaipropertynews.com\/feeds\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=15362"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/thaipropertynews.com\/feeds\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=15362"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/thaipropertynews.com\/feeds\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=15362"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}